1. Field of Invention
The invention relates to a test circuit, and in particular to a test circuit that is applicable for system-on-a-chip and compliant with IEEE 1500 standard.
2. Related Art
Continuous development of integrated circuits has increased in the chip integrity such that integrating a complicated system on an independent System-On-a-Chip (SOC) has become an economic and feasible scheme. Chip integrated applications have thus also increased. System-On-a-Chip combines core circuits, such as microprocessor, digital signal processor (DSP), memory, digital to analog converter (DAC), analog to digital converter (ADC), phase lock loop (PLL), logic circuits and so on. However, the fault coverage greatly decreases. For verifying oneness of chips effectively, the Institute of Electrical & Electronic Engineers (IEEE) has provided a test standard: IEEE 1500 for System-On-a-Chip to solve the problem of low fault coverage.
The purpose of the IEEE 1500 standard is to define a standard test interface for the core circuits. The standard (a) defines the test interface between core circuits; (b) establish an access and isolation mechanism for core circuits such that the test patterns and procedures designed for these core circuits may be reused; (c) is capable of testing the interconnections between core circuits and testing User-Defined Logic (UDL); (d) integrates the core circuits compliant with IEEE 1500 standard into System-On-a-Chip by way of plug-and-play, and the testing between core circuits is need to cooperate with one another.
However, IEEE 1500 only establishes a standard for the test access and isolation mechanism including control mechanism of pin protocols and test modes for core circuits. However, the architecture of the test access mechanism (TAM) of the system is reserved for system developers. Furthermore, the test scheme of the core circuits such as BIST or scan is reserved for core designers. IEEE 1500 is in charge of supporting, activating, and controlling these test circuits for test operations.
In the test scheme of IEEE 1500, the core circuits could be tested with the IEEE 1500 standard wrapper through the standard test interface such as WSI/WSO, and the I/O ports of the test access mechanism (TAM-source, TAM-link). The test data is delivered to the core circuit by way of TAM-source and/or WSI 101, and the test results are outputted from TAM-sink and/or WSO 103. The control signals necessary for the test data transfer are provided by a central test controller.
FIG. 1 illustrates the test scheme. The test wrapper includes four registers 11˜14, multiplexers 15˜16, a bypass register 17, a Wrapper Instruction Register decoder 18 (WIR decoder), and an instruction register 19 (Wrapper Instruction Register, WIR) to test the core circuit 10. The registers 11˜14 are Wrapper Boundary Registers (WBR), each composed of a plurality of Wrapper Boundary Cells (WBC). The number of the Wrapper Boundary Cells corresponds to the I/O ports of a core. The instruction 19 is a multi-bit register which length depending on how many bits that the wrapper test instruction is defined.
The data path starts from Wrapper Serial Input (WSI) 101 to Wrapper Serial output (WSO) 103 passing through registers and multiplexers.
To elaborate on the test procedure in more detailed, please refer to FIG. 2. WBR 130, 132 are disposed corresponding to input ports 110 and output ports 112 of the core circuit 10. A controller (not shown in the figure) outputs control signals and test signals for the core circuit 10 to be tested. The control signals are outputted via SelectWIR, ShiftWR 120, UpdateWR 122 and CaptureWR 124. The test signals are outputted via WSI 101 for WBR, Bypass Register 140 and WIR 142. The controller also outputs clock signals via WRCK 126 (Wrapper Clock) for WBR, Bypass Register 140 and WIR 142. The WIR decoder 144 decodes the test instruction inside the WIR 142 to control a multiplexer 150. SelectWIR 148 is used to control a multiplexer 152 to decide which signal to be outputted to the WSO 103 as the result signals. The WSO 103 is controlled by the multiplexer 150 and 152 which are controlled by WIR decoder 144 and SelectWIR 148. Because the controller does not directly control multiplexers 150 and 152, the controller should compile the test into the corresponding instruction and send the instruction to WIR 142 through WSI 101 at the beginning of each test (this will be depicted in the followings).
FIG. 3 illustrates a timing diagram for one single core circuit tested with a two-step test and an IEEE 1500 standard complinant wrapper. Please refer to FIG. 2 and FIG. 3 simultaneously. When the controller proceeds a bypass test 150, the controller should do operations of instruction 160a and execution 162a. The controller at first compiles of the bypass test into bypass instruction 161a, sends out the bypass instruction 161a through WSI 101 into WIR 142 to do 160a instruction operation and then sends control 163 signals of execution via ShiftWR 120, UpdateWR 122 and CaptureWR 124 for the bypass register 17 to do execution 162a operation. Sending the bypass instruction 161a into WIR 142 usually takes a few clocks, for example 4 clocks, depending on how many bits the WIR 142 has. When the controller controls the core circuit 10 to do a WCORETEST 152 test, the controller should proceed at least the following operations in sequence: instruction 160b, scan-in 164, execution 162b and scan-out 168. As shown in FIG. 3, the operation of execution 162b originally takes two or more clocks depending on the design of test controller. In practical, the operation of execution 162b takes only one clock owing that the test signals 165 in the next operation (scan 166) is pushed ahead one clock as shown in WSI. That means the test signals 165 in scan 166 operation are not sent at the beginning (the first clock) of scan 166 operation, but are sent one clock ahead of the beginning of the scan 166 operation. If the WCORETEST is a two-step test procedure, the controller proceeds the following operations in sequence: instruction 160b, scan-in 164, execution 162b, scan 166, execution 162c and scan-out 168. In other words, the two-step test procedure needs one more scan 166 and one more execution 162c operations to be inserted behind the execution 162b. Consequently, a three-step test procedure of WCORETEST should proceed instruction 160b, scan-in 164, execution 162b, scan 166, execution 162c, scan 166, execution 162c, scan-out 168.
When the controller proceeds the instruction 160a or the scan 166 operation, the ShiftWR 120 of control signals 163 should be at high level as well as the UpdateWR 122 and CaptureWR 124 should be at low level. When the controller proceeds the execution 162a operation, the UpdateWR 122 should be at high level in the first clock followed by CaptureWR 124 at high level.
Please refer to FIG. 2 again. Another core circuit 10′ (shown in dotted lines) is disposed next to the core circuit 10. The another core circuit 10′ has its own test circuits which are the same as that of the core circuit 10 and connected to the core circuit 10′. These two core circuits 10, 10′ are controlled by the same controller. If there are five core circuits, the five core circuits are connected in serial. Practically, a controller controls a few hundreds of core circuits at the same time.
Please continuously refer to FIG. 4 illustrating a timing chart for three core circuits tested with a two-step test procedure according to IEEE 1500 standard. If the three core circuits are tested with a two-step test procedure, most operations in FIG. 4 are three times in clock length than the operations in FIG. 3. The instructions 180a, 180b are three times in clock length than the instructions 160a, 160b in FIG. 3. The execution 182a, 182b, 182c is three times in clock length than the execution 162a in FIG. 3. The scan-in 184, scan 186 and scan-out 188 are also three times in clock length than the scan-in 164, scan 166 and scan-out 168.
IEEE 1500 defines test wrappers, which have a plurality of instruction registers, surrounding the core circuits to control the boundary scan circuits. However, as depicted as above, the more core circuits are tested simultaneously, the more time it takes. This increases the test time and test cost. Therefore, there is an urgent need to provide a test scheme to reduce the test time and cost effectively.
Furthermore, System-On-a-Chip has more advantages in terms of weight, volume, performance, and price than the conventional circuit board systems. If the testing scheme is not taken into consideration with system design, the test cost may exceed the manufacturing cost during mass production because the testing time is propositional to the circuit scale. Therefore, the test scheme for development of System-On-a-Chip is a main point during system design.